1/4 rev. e structure silicon monolithic integrated circuit type regulator ic fo r memory termination product series bd3533hfn features ? incorporates a push-pull power supply for termination (vtt) ? incorporates a reference voltage circuit(vref) ? compatible with dual channel (ddr- ) absolute maximum ratings (ta=100 ) parameter symbol limit unit input voltage vcc 7 *1*2 v enable input voltage ven 7 *1*2 v termination input voltage vtt_in 7 *1*2 v vddq reference voltage vddq 7 *1*2 v output current itt 1 a power dissipation1 pd1 630 * 3 mw power dissipation2 pd2 1350 * 4 mw power dissipation3 pd3 1750 * 5 mw operating temperature range topr -30 +100 storage temperature range tstg -55 +150 maximum junction temperature tjmax +150 *1 should not exceed pd. *2 instantaneous surge voltage, back electromotive force and voltage under less than 10% duty cycle. *3 with ta R 25 when mounting a 70mm 70mm 1.6mm glass-epoxy substrate 1-laye r board (copper foil density 0.2%) ja=198.4 / *4 with ta R 25 when mounting a 70mm 70mm 1.6mm glass-epoxy subs trate 1-layer board (copper foil density 7%) ja=92.4 / *5 with ta R 25 when mounting a 70mm 70mm 1.6mm glass-epoxy subs trate 1-layer board (copper foil density 65%) ja=71.4 / recommended operating conditions (ta=25 ) parameter symbol min max unit input voltage vcc 2.7 5.5 v termination input voltage vtt_in 1.0 5.5 v vddq reference voltage vddq 1.0 2.75 v enable input voltage ven -0.3 5.5 v no radiation-resistant design is adopted for the present product. the japanese version of this docume nt is the official specification. this translated version is intended only as a refere nce, to aid in understanding the official version. if there are any differences between the original and translated versions of this document, the official japanese language vers ion takes priority.
2/4 rev. e electrical characteristics (unless otherwise specified,ta=25 vcc=3.3v ven=3v vddq=1.8v vtt_in=1.8v) parameter symbol limit unit conditions min typ max standby current ist - 0.5 1.0 ma ven=0v bias current icc - 2 4 ma ven=3v [enable] high level enable input voltage venhigh 2.3 - 5.5 v low level enable input voltage venlow -0.3 - 0.8 v enable pin input current ien - 7 10 ua ven=3v [termination] termination output voltage 1 vtt1 vref-30m vref vref+30m v itt=-1.0a to 1.0a ta = 0 to 100 *6 termination output voltage 2 vtt2 vref-30m vref vref+30m v vcc=5v, vddq=2.5v vtt_in=2.5v itt=-1.0a to 1.0a ta = 0 to 100 *6 source current itt+ 1.0 - - a sink current itt- - - -1.0 a load regulation S vtt - - 50 mv itt=-1.0a to 1.0a line regulation reg.l - 20 40 mv upper side on resistance 1 hron1 - 0.45 0.9 lower side on resistance 1 lron1 - 0.45 0.9 upper side on resistance 2 hron2 - 0.4 0.8 vcc=5v, vddq=2.5v vtt_in=2.5v lower side on resistance 2 lron2 - 0.4 0.8 vcc=5v, vddq=2.5v vtt_in=2.5v [input of reference voltage] input impedance zvddq 70 100 130 k [reference voltage] output voltage 1 vref1 1/2 vddq -18m 1/2 vddq 1/2 vddq +18m v iref=-5ma to 5ma ta = 0 to 100 *6 output voltage 2 vref2 1/2 vddq -40m 1/2 vddq 1/2 vddq +40m v iref=-10ma to 10ma ta = 0 to 100 *6 output voltage 3 vref3 1/2 vddq -25m 1/2 vddq 1/2 vddq +25m v vcc=5v, vddq=2.5v vtt_in=2.5v iref=-5ma to 5ma ta = 0 to 100 *6 output voltage 4 vref4 1/2 vddq -40m 1/2 vddq 1/2 vddq +40m v vcc=5v, vddq=2.5v vtt_in=2.5v iref=-10ma to 10ma ta = 0 to 100 *6 [uvlo] uvlo off voltage vuvlo 2.40 2.55 2.70 v vcc : sweep up hysteresis voltage S vuvlo 100 160 220 mv vcc : sweep down *6 design guarantee
3/4 rev. e physical dimensions block diagram pin number pin name pin no. pin name 1 gnd 2 en 3 vtts 4 vref 5 vddq 6 vcc 7 vtt_in 8 vtt fin vcc vcc vddq vddq vcc vtt vtts en enable reference block thermal protection gnd vtt vref ? vddq vtt_in tsd en uvlo vtt_in uvlo tsd vcc vcc uvlo vcc tsd en uvlo en soft tsd en uvlo 1 2 6 5 7 3 4 - + - + + - 8 c2 c3 c4 c1 hson8 (unit:mm) b d 3 5 3 3 1pin mark lot no.
4/4 rev. e notes for use (1) absolute maximum range although the quality of this product is rigorously controlled, and circuit operation is guaranteed within the operation ambient temperature range, the device may be destroyed when applied vo ltage or operating temperature exceeds its absolute maximum rating. because the failure mode (such as s hort mode or open mode) cannot be identified in this instance, it is important to ta ke physical safety measures such as fusing if a specific mode in excess of absolute ra ting limits is considered for implementation . (2) ground potential make sure the potential for the gnd pin is always kept lower than the potentials of all other pins, regardless of the operating mode, including trans ient conditions. (3) thermal design provide sufficient margin in the thermal design to account for the allowable power dissipation (p d) expected in actual use. (4) using in the strong electromagnetic field use in strong electromagnetic fi elds may cause malfunctions. (5) aso be sure that the output transistor for this ic does no t exceed the absolute maximum ratings or aso value. (6) thermal shutdown circuit the ic is provided with a built-in thermal shutdown (tsd) ci rcuit. when chip temperature reaches the threshold temperature shown below, output goes to a cut-off (open) state. note that t he tsd circuit is designed exclusiv ely to shut down the ic in abnormal thermal conditions. it is not intended to protect the ic per se or guarantee performance when extreme heat occurs. therefore, the tsd circuit should not be employed with the ex pectation of continued use or s ubsequent operation once tsd is operated. (7) gnd pattern when both a small-signal gnd and high current gnd are presen t, single-point grounding (at the set standard point) is recommended, in order to separate the small-signal and high current patterns, and to be sure the voltage change stemming from the wiring resistance and high current does not cause any voltage change in the small-signal gnd. in the same way, care must be taken to avoid wiring pattern fluctuati ons in any connected external component gnd. (8) output capacitor (c1) mount an output capacitor between vref and gnd for stability pu rposes. the vref output capaci tor is for the open loop gain phase compensation. if the capacitor value is not large enough, the output voltage may oscillate. a ceramic 1.0 - 10uf capacito r with minimal susceptibility to temperature is recommended. however, this stability depends on the characteristics of temperature and load. please confirm operation acro ss a variety of temperature and load conditions. (9) output capacitor (c4) mount an output capacitor between vtt and gnd for stability pu rposes. the output capacitor is for the open loop gain phase compensation and reduces the output voltage load regulation. if the capacitor value is not large enough, the output voltage may oscillate. and if the equivalent series resistance (esr) is too large, the output voltage rise/drop increases during a sudden l oad change. a 47 - 220uf polymer capacitor is recommended. however, the stability depends on the characteristics of temperature and load conditions. and if a small esr capacitor such as a ce ramic capacitor is utilized, the output voltage may oscillate due to lack of phase margin. in this case, measures can be taken by addi ng a resistor in series with this capacitor. please confirm operation across a variety of temperature and load conditions. (10) input capacitor (c2, c3) the input capacitor reduces the output impedence of the volt age supply source connected in the vcc and vtt_in. if the output impedence of this power supply increases, the input voltage (vcc,v tt_in) may become unstable. this may result in the output voltage oscillation or lowering ripple rejection. a low esr 1uf capacitor in vcc and 10uf capacitor in vtt_in with minimal susceptibility to temperature are preferable, but stability depen ds on power supply characterist ics and the substrate wiring pattern (a parasitic capacitance and im pedance). please confirm operation across a vari ety of temperature and load conditions. (11) input vcc, vddq, vtt_in, en the vcc, vddq, vtt_in, and en are isolated. the uvlo function is integrated to protect faulty operation due to low voltage levels of vcc. vtt output voltage starts up when vcc reaches the uvlo threshold level and en reaches the threshold level respectively regardless of the start up order in those inputs. and also vref output voltage starts up when vcc reaches the uvlo threshold level. when the vddq and vtt_in has the same voltage and are supposed to connect each other, vddq pin voltage may change due to the voltage drop on the vtt_in and vddq common wiring caused by vtt_in input current change. this may result in the voltage change of the vtt output. avoid drawing wiring pattern of vddq and vtt_in so that they do not have common wiring. if the common wiring is inevitable due to lim ited pcb area, it is recommended that cr filter be added between vtt_in and vddq. (12) vtts vtts is to improve load regulation of vtt output. for precise load regulation, vtts is connected close by vtt to avoid common impedance. (13) heat sink (fin) since the heat sink (fin) is connected wi th the sub, short it to the gnd. it is possible to minimize the thermal resist ance by soldering it to gnd plane of pcb. (14) short-circuits between pins and and mounting errors do not short-circuit between output pin (vo) and supply pin (vcc) or ground (gnd), or between supply pin (vcc) and ground (gnd). mounting errors, such as incorrect posit ioning or orientation, may destroy the device. (15) please add a protection diode when a la rge inductance component is connected to the output terminal, and reverse-polarity power is possible at startup or in output off condition tsd on temperature [ ] (typ.) hysteresis temperature [ ] (typ.) 175 15 (example) output pin
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